DIMM Ranking

The number of ranks on any DIMM is the number of independent sets of DRAMs that can be accessed simultaneously for the full data bit-width of the DIMM to be driven on the bus. The physical layout of the DRAM chips on the DIMM itself does not necessarily relate to the number of ranks. Sometimes the layout of all DRAM on one side of the DIMM PCB versus both sides is referred to as "single-sided" versus "double-sided".

These terms may cause confusion as they do not necessarily relate to how the DIMMs are logically organized or accessed.

For example, on a single rank DIMM that has 64 data bits of I/O pins, there is only one set of DRAMs that are turned on to drive a read or receive a write on all 64-bits. In most electronic systems, memory controllers are designed to access the full data bus width of the memory module at the same time.

On a 64-bit (non-ECC) DIMM made with two ranks, there would be two sets of DRAM that could be accessed at different times. Only one of the ranks can be accessed at a time, since the DRAM data bits are tied together for two loads on the DIMM (Wired OR). Ranks are accessed through chip selects (CS). Thus for a two rank module, the two DRAMs with data bits tied together may be accessed by a CS per DRAM (e.g. CS0 goes to one DRAM chip and CS1 goes to the other). DIMMs are currently being commonly manufactured with up to four ranks per module.

Consumer DIMM vendors have recently begun to distinguish between single and dual ranked DIMMs. JEDEC decided that the terms "dual-sided," "double-sided," or "dual-banked" were not correct when applied to registered DIMMs.